Support of Delay and Jitter Requirements

Participants: Cesnet, ENST Bretagne, GARR, GRnet, INFN-CNAF, Poznan Supercomputing & Networking Center
Coordinator: T.Ferrari, INFN-CNAF


Programme

  1. Per-class shaping:

  2. High-speed to low-speed:
    1. GOAL:
      verify the impact on the microflow delay and jitter profile of devices (e.g. at diffserv domain boundaries) forwarding traffic from an input high-speed interface to an output lower-speed output interface
    2. TIMELINE: 1st Q 2001
    3. PROGRAMME:
      Analysis of the delay and jitter frequency distributions of packets of a given microflow when coming from a high-speed interface to a lower-speed interface.
      The experiment can be repeated for different input rate/output rate ratios
    4. REQUIREMENTS:
      1. production traffic for background and reference-class traffic; reference microflow injected by specialized device for precise delay and jitter estimation;
      2. Input: STM-16; Output: STM-4 and lower

  3. Deaggregation:
    1. GOAL:
      verify the impact of one or multiple deaggregation points on the data path of a given micro-flow
    2. TIMELINE: 1st and 2nd Q 2001
    3. PROGRAMME:
      1. testbed configuration with multiple hops;
      2. definition of traffic patterns so that a given micro-flow traverses alternatively multiple aggregation/deaggregation points
      3. reference microflow: injected by specialized hardware
    4. REQUIREMENTS:
      1. background and reference-class production traffic

  4. Per-microflow end-to-end performance within a traffic aggregate (Tijani Chahed)

  5. Enforcement of delay and jitter-guarantees:


Last modified: Oct 12 2001, Tiziana Ferrari